(a) Field of the Invention
The present invention relates to a digital phase locked loop (PLL) circuit and, more particularly, to a digital PLL circuit for generating a clock signal used for synchronization between semiconductor integrated circuits.
(b) Description of the Related Art
PLL circuits are generally used to generate an internal clock signal which is in phase with an input reference clock signal. A digital PLL circuit disposed in a semiconductor integrated circuit receives a reference clock signal and generates an internal clock signal therefrom, and feeds-back the internal clock signal to synchronize the internal clock signal with the reference clock signal.
FIG. 1 shows a conventional digital PLL circuit, which comprises a phase comparator 51, a delay controller 52 and a variable delay circuit 53. The phase comparator 51 compares the phase of a reference clock signal CLK against the phase of an internal clock signal ICK in synchrony with the clock of the reference clock signal CLK to generate a phase lead/lag signal PD representing the result of the comparison. The delay controller 52 responds to an enable signal not shown and the phase lead/lag signal to output a delay control signal CNT by effecting increment or decrement of a previous delay control signal based on the phase lead/lag. The variable delay circuit 53 generates a delay on the reference clock signal CLK based on the amount specified by the delay control signal CNT to generate the internal clock signal ICK.
The conventional digital PLL circuit of FIG. 1 operates for synchronization by controlling the delay time in the variable delay circuit even when only a small difference exists between the phases of the reference clock signal and the internal clock signal. The small phase difference may result from small fluctuation of the internal clock signal due to the coupling between the internal clock line and adjacent signal lines and does not affect the normal operation of the integrated circuit. Similar situation occurs upon an external factor wherein the reference clock signal has a small jitter. These synchronization operations result in excess power dissipation in the semiconductor device.
In addition, if the internal or external factor which has delayed, for example, the internal clock signal disappears in a short time and yet the PLL circuit operates for synchronization by advancing the internal clock signal, the phase shift rather increases after the synchronization. To solve the above problem, it is proposed that the digital PLL circuit operate for synchronization only when the phase lag is detected at successive two or more cycles of the reference clock signal.
FIG. 2 shows a synchronization circuit described in Patent Publication JP-A-1(1989)-93280 for solving the problem described for the conventional PLL circuit. The synchronization circuit comprises a synchronizing signal detecting block, including a shift register 503, a latch circuit 504 and a timing generator 507, for detecting an original super-frame synchronizing signal "b" and a mode-changeover synchronizing signal based on a bit stream signal etc. supplied from a BS tuner not shown.
A frequency divider 510 having a divisional ratio of nine and a synchronization circuit 508 constitute a PLL circuit, wherein the frequency divider 510 functions as a variable delay circuit, for comparing the original super-frame synchronizing signal "b" against the output "c" of the frequency divider 510 to output a super-frame synchronizing signal as an output from the synchronization circuit 508 upon detection of a phase shift at a specified number of successive times. Similarly, a frequency divider 512 having a divisional ratio of ten and a synchronization circuit 509 constitutes another PLL circuit which outputs a mode-changeover synchronizing signal.
The PLL circuits as described above supply stable outputs as the super-frame synchronizing signal and mode-changeover synchronizing signal based on the frame synchronizing signal "a", even when the bit stream signal is attenuated to generate an error in a frame controller for the bit stream signal for a specified number (three, for example) of times in the satellite broadcast communication.
If a phase difference between the external clock signal and the fed-back internal clock signal exceeds a threshold in the circuit of FIG. 5, the large phase difference should be removed as quickly as possible. However, the PLL circuits operate after the phase difference is detected for the specified number of times, which consumes a longer time for synchronization, and may cause a serious problem in the operation of the semiconductor device.